A digital application specific integrated circuit (ASIC) typically includes both combinational and sequential logic. The sequential logic (e.g., registers, state machines, etc.) is usually designed with flip-flops (FFs). When first powering up such a circuit, the default states of all the flip-flops need to be defined to set the ASIC into a known initialized state. Furthermore, this initialization must be accomplished in a consistent fashion each time the circuit is powered up. For example, finite state machines (FSM) need to be consistently reset to predefined start-up states, interrupt registers and mask registers need to be consistently initialized to correct states, etc.
A reset signal, often referred to as a system reset (SysReset) signal, is typically employed to initialize the logic. Normally, the SysReset signal is generated automatically when the ASIC or device that contains the ASIC is powered up. For example, when a cellular telephone is first powered on, the telephone's digital circuitry is reset and initialized to a known state. The SysReset can also be generated for other reasons so as to place the device into a default state. For example, many personal computers have a front panel reset button which, when depressed, causes the computer to re-initialize as though the power were switched off and then on again.
The SysReset can be applied to the flip-flops either synchronously or asynchronously. If an asynchronous reset is used, the SysReset is typically connected either to a reset (RST) input or to a preset (SET) input of each flip-flop. In each case there are setup and hold time requirements for the SysReset release timing, referenced to a rising edge of a clock (CLK) input of the flip-flop. The setup time for a flip-flop input defines a time window within which the input must be stable before the rising edge occurs at the flip-flop CLK input. Similarly, the hold time for a flip-flop input defines the time window during which the input must be stable after the rising edge has occurred at the flip-flop CLK input. The setup and hold time requirements vary according to the flip-flop type, flip-flop input, technology (e.g., CMOS vs. bipolar), etc., but typically the setup and hold time requirements are on the order of a few nanoseconds.
If the setup and hold time requirements are not fulfilled when deactivating the SysReset, it is possible that the flip-flop has not been initialized to the desired state. To prevent such an initialization failure, it is important that the SysReset not be released at about the same time that a rising edge occurs in the flip-flop's CLK input.
A traditional method to release the SysReset is to use a system clock rising edge (thus fulfilling the setup time requirement), and to add a delay element to delay the SysReset deactivation sufficiently to fulfil the hold time requirement.
FIG. 1A illustrates a conventional circuit using two flip-flops (FF1 and FF2) and a delay element to generate the SysReset signal from a stimulus signal such as a Power On Indication signal (typically generated by a power supply that powers the circuit), and to apply it asynchronously on and synchronously off. FIG. 1B illustrates the associated waveforms. The Power On Indication signal is assumed for this example to be active low (designated by the *).
This method is practical when the clock frequency is low, and where there are only a few clocks used in the design. In other words, this approach can be utilized when it is possible to find a time window in which to deactivate the SysReset, while still fulfilling the setup and hold time requirements of the flip-flops being initialized.
However, when the clock frequency is increased and when several clocks, including delayed clocks, are used in the design, the approach shown in FIGS. 1A and 1B is no longer reliable. This is because the rising edges of the various different clocks will occur at different times. For example, a clock skew caused by clock tree delays will introduce a temporal variation in the rising edges of the same clock occurring in different blocks of logic. In addition, if inverted and delayed clocks (created from the System Clock with delay elements) are used, there will be even more rising edges occurring in the time domain.
Depending on operating conditions, the best and worst case (min and max) clock delay values can vary considerably. As a result, it may simply be impossible to find a "clock edge free" time window that is sufficiently long to release the SysReset signal, while still fulfilling the setup and hold time requirements of all circuit flip-flops under all operating conditions.
Furthermore, and as is well appreciated by those skilled in the art, the use of delay elements is often undesirable, either because of excessive cost, if discrete delay element circuits are employed, or because of unreliability if the delays inherent in series coupled gates or buffers are employed.